1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device and a method for manufacturing the same in which copper is prevented from being exposed to a surface of a passivation film after a Cu metal line formation, to avoid contaminating equipment or the process environment.
2. Discussion of the Related Art
With more highly integrated semiconductor devices, the parasitic capacitance of a dielectric film and the resistance of a metal line both increase. Increased parasitic capacitance and resistance together slow the operational speed of a device. Therefore, there has been a trend toward the use of lower-k dielectrics as an interlayer dielectric film and the use of copper, which has low resistance, for metal lines. For bonding pads, however, aluminum is typically deposited on a copper wiring layer, since copper is a poor alloy with gold and is thus unsuitable for bonding pad formation. Such a process requires two separate passivation steps, whereby a passivation film is formed to prevent water penetration or corrosion during processing. Therefore, each passivation film must be without defects such as cracking and lifting. For example, defects in the passivation film may occur due to stresses generated when of scribing the wafer to render a plurality of devices or chips. Scribing typically uses an alignment key formed of fine copper patterns positioned in a scribe lane.
In a process of passivation film formation, a passivation film of a scribe lane is removed to guard against defects caused by such stressing. However, the copper lines of the alignment key are exposed, leading to potential contamination of equipment or the process environment during subsequent processing.
FIGS. 1A-1E respectively illustrate a method for manufacturing a semiconductor device according to a related art. As shown in each drawing, a semiconductor substrate is provided with a chip area (left side) and a scribe lane (right side). In the chip area, each of a plurality of metal wiring layers may be formed on a corresponding number of dielectric films. In FIGS. 1A-1E, the final layer of dielectric and metal line formation is depicted.
As shown in FIG. 1A, a dielectric film 1 is finally deposited on a semiconductor substrate (not shown) in which a number of metal wiring layers are formed using, for example, a damascene process. A first conductive film 2 is formed in the chip area over the last of the dielectric layers. Thus, the first conductive film 2 represents the final or uppermost metal wiring layer. Then, a first passivation film 3 is deposited on an entire surface of the substrate including the first conductive film 2.
Then, an alignment mark 5, which is a very fine pattern for aligning a wafer during processing, is formed in the scribe lane. The conductive film 2 and the alignment mark 5 are both formed of copper.
As shown in FIG. 1B, a first photoresist 4 is deposited on the first passivation film 3 and is patterned by a predetermined photolithography process. Using the first photoresist 4 as a mask, the first passivation film 3 is etched in the chip area to expose a portion, such as a bonding pad area, of the first conductive film 2 and is etched in the scribe lane to expose the alignment mark 5.
As shown in FIG. 1C, after the first photoresist 4 is removed, a second conductive film 6 is deposited on the entire surface and patterned by photolithographic and etching processes to remain on the portion, such as the bonding pad area. The second conductive film 6 is formed of aluminum.
As shown in FIG. 1D, a second passivation film 7 is deposited on the entire surface of the substrate including the second conductive film 6. A second photoresist 8 is deposited on the second passivation film 7 and patterned by photolithography to expose a bonding pad area and the scribe lane.
As shown in FIG. 1E, the second passivation film 7 is selectively etched using the second photoresist 8 as a mask to expose a portion of the second conductive film 6. The second photoresist 8 is then removed. The alignment mark 5 in the scribe lane is also exposed.
When a chip is finally cut, i.e., after completing an entire process of manufacturing a semiconductor device, a passivation film in a scribe lane is removed so as not to generate a defect caused by stress in the passivation film. A copper alignment mark, exposed as a result of the removal of the passivation film in the scribe lane, may contaminate equipment or cause fatal defects, as shown in FIG. 2.